cache memory
英 [kæʃ ˈmeməri]
美 [kæʃ ˈmeməri]
网络 缓存内存; 高速缓存; 高速缓冲存储器; 快取内存; 快取記憶體
双语例句
- In a traditional application server environment, cache memory is contained within each application server instance.
在传统应用程序服务器环境中，缓存内存包含在每个应用程序服务器实例中。 - Cache memory is much smaller and faster than main memory and can either be internal or external to the processor chip.
它可以在处理器芯片的内部，也可以在处理器芯片的外部。 - This makes it very similar to caching operations, where blocks of instructions are moved from memory into a local fast cache memory for execution.
这使它与缓存操作非常类似，后者是将指令块从内存移动到本地快速缓存中执行。 - Caching these pages in a page response cache that is shared by multiple users would quickly consume the cache memory but would not result in many cache hits.
如果将这些页面缓存在多个用户共享的页面响应缓存中，则可能会很快用完缓存内存，却不能提高缓存命中率。 - OProfile analysis: Cache memory utilization problem
Oprofile分析：高速缓存利用率问题 - When the CPU reads data from main memory, a copy of this data is stored in the cache memory.
当CPU从主内存中读取数据时，一份数据拷贝将被存储在高速缓存中。 - General register unit The fastest memory is known as cache memory and is what it sounds like-memory that is used to temporarily hold, or cache, contents of the main memory.
通用寄存器单元-用以存储微程序的暂时存储区最快的的存储器是高速缓存，它被用来暂存主存中的内容。 - Finally there is the main memory which relative to the external cache memory is very slow. It has made a great progress since the successful cryopreservation of mouse embryos in 1972.
这样，相对外部高速缓存存储器，主存的速度非常慢。自20世纪70年代对小鼠胚胎冻存成功以来，胚胎冷冻技术已得到飞速发展。 - Because memory logically divided on buffer or cache memory and firmware memory.
因为从逻辑上划分内存缓冲区或高速缓存内存和固件的内存。 - The digital video signals bit plane separation strategy is applied in the circuit design, and the sub-field writing-in and sub-area readout to the cache memory method is used.
该电路的设计，应用了数字视频数据信号位面分离的策略，采用了分场写入、分区读出缓存存储器的方法。 - Bytes of cache memory in use by the server for burst buffers
服务器用于快速缓冲区的高速缓存字节数 - Design of high speed and large scale FIFO cache memory
高速大容量FIFO缓冲存储器设计 - The next time the CPU reads the same address, the data is transferred from the cache memory instead of from main memory.
当CPU下次读取相同地址时，数据将从高度缓存中而不是主存储器中传出。 - This high speed cache memory eliminates the CPU wait state.
这种高速缓存降低了CPU等待时间。 - Cache memory control communication
高速缓冲存储器控制通信 - When CPU read Cache data, it compared the highest position of physical address with corresponding address label of symbol memory at first to determine whether the data in cache memory should be sent to CPU directly.
当CPU读取Cache的数据时，先将物理地址的最高位与标志存储器中对应地址标签比较。判断是否将数据总线直接传送给CPU。 - BUFFER CAPACITY Experimental study of optical parallel cache memory arrays
光学并行高速缓冲存储列阵的实验研究 - The Effects of Locality of Reference in Cache Memory System
访问局部性原理在Cache存储系统中的作用 - This article introduces the working principle of Cache memory system and its function in raising the system perormance;
简单介绍了Cache存储系统的工作原理以及它在提高系统性能方面的作用； - We realized a 2-level storage system including a cache memory, a main memory and the memory control interface between the storage system and the pipeline core.
本文实现了二级存储系统。存储系统包括Cache存储器、主存和存储系统与流水线核之间的存控接口。 - Analysis of Computer Cache Memory Architecture
计算机高速缓冲存储器体系结构分析 - This article probes into the applications of locality of principle in the design and optimize_strategies of Cache memory system.
讨论了访问局部性原理在Cache存储系统中的体系结构设计和优化策略中的应用。 - NET executive process, efficiency and cache memory technique, introduces performance optimization methods to exploit Web application program with ASP. NET.
NET的执行过程、效率以及缓存技术，介绍了利用ASP.NET开发Web应用程序的性能优化方法。 - Modern microprocessors which use Cache memory system and instruction pre-fetching increase the difficulty to compute the upper bound accurately.
由于现代微处理器使用了基于Cache存储和指令预取技术，增加了准确确定这一上界的难度，为此提出了一种基于指令Cache和指令预取联合模型的嵌入式软件性能评估新方法。 - In this paper, we briefly survey architectural techniques for high performance and low power cache memory.
着重讨论了体系结构级的高性能低功耗Cache存储器的相关技术。 - A specific test chip design plan has been proposed for the RDS module, level-one and level-two cache memory.
为RDS模块、一级Cache和二级Cache的存储体提出并实现了一种专用的测试芯片设计方案，完成了电路设计与版图设计。 - Based on the embedding in the local one-dimensional search algorithm for hybrid particle swarm optimization the cache memory parameters were optimized, and was proved its applicability.
在此基础上提出嵌入局部一维搜索的混合粒子群优化算法对内存缓存的开启参数进行了优化，并证明了其适用性。 - Base on Cache system, proposes the data reload strategy which using cyclic redundancy codes. Implements the high reliability Cache controller which using cyclic redundancy codes to check error in Cache memory and data reload to correct the error. 4.
三.根据Cache系统的情况，提出了基于循环码校验的数据重载策略，实现了用循环码来检测Cache中的错误并通过数据重载更新错误数据的高可靠Cache控制器。 - This thesis is based on a DSP design project in XX research institute, including two parts of work: cache controller design and cache memory design.
本文的研究工作以XX研究所的xxDSP项目为基础，分为两个部分：cache控制器设计和cache存储器的设计。 - Now, SRAM can be designed using full-custom, which can improve the performance of SRAM and overcome the bottle-neck problem induced by unmatchable speed when micro processor access to the cache memory.
目前，通常采用全定制方法对SRAM进行专门设计和优化，使SRAM性能得到进一步提高，以缓解微处理器访问高速缓存时因速度不匹配而引起的访存瓶颈问题。